1. Field of the Invention
This invention generally relates to a pixel structure for a thin film transistor array and a fabricating method thereof, and more particularly to a pixel structure and a fabricating method thereof to prevent the pixel storage capacitor from leakage.
2. Description of the Related Art
A thin film transistor liquid crystal display (TFT LCD) includes a thin film transistor array, a color filter array, and a liquid crystal layer. The thin film transistor array includes a plurality of thin film transistors arranged in arrays and a plurality of pixel electrodes corresponding to the plurality of thin film transistors to form a plurality of pixel structures. The thin film transistor includes a gate electrode, a channel, a source electrode, and a drain electrode, which is the switch of the liquid crystal display unit.
FIG. 1 is the top view of a pixel structure of the conventional TFT array. This pixel structure is set on a substrate (not shown) and includes a gate line 102, a data line 104, a thin film transistor 130, a pixel storage capacitor 116 and a pixel electrode 112.
The thin film transistor 130 includes a gate electrode 106, a channel layer 108, a source electrode 110a and a drain electrode 110b. The gate electrode 106 is electrically connected to the gate line 102. The source electrode 110a is electrically connected to the data line 104. The drain 110b is electrically connected to the pixel electrode 112 through the contact window 114.
The pixel storage capacitor 116 includes a bottom electrode 118, a top electrode 120, and a dielectric layer between the bottom electrode 118 and the top electrode 120. The top electrode 120 is electrically connected to the pixel electrode 112 through the contact window 122. The bottom electrode 118 is a common line, and is in the Metal 1 layer as same as the gate line 102 and the gate electrode 106. The top electrode 120, the data line 104, and the source/drain electrodes are in the Metal 2 layer. A gate insulating layer (not shown) is disposed between the Metal 1 and Metal 2 layers. A passivation layer (not shown) is disposed between the Metal 2 layer and the pixel electrode 112.
It should be noted that there are terminals at the two edges of the substrate (not shown) to electrically connect the driver circuit. Those terminals are a part of the Metal 1 layer, and the data line 104 and the gate line 102 extending to the edges of the substrate are electrically connected to the terminals.
To expose the terminals for connecting the driver circuit, the gate insulating layer and the passivation above the terminals have to be etched. However, to expose the contact windows 114 and 122, only the passivation layer has to be etched, especially to expose the contact window 122. Because the contact window 122 is above the pixel storage capacitor 116, if the gate insulating layer is etched away, it will cause leakage between the top electrode 118 and the bottom electrode 120 of the capacitor 116. Hence, the steps of etching the passivation layer and the gate insulating layer are very critical to TFT manufacturing processes.
A conventional method to overcome the above problem is to form an amorphous silicon layer below the contact window, which is defined by the channel layer of the thin film transistor. This method uses the amorphous silicon layer as a stop layer to prevent the gate insulating layer below the contact window from etching through. However, the etch selectivity between the amorphous silicon layer and the gate insulating layer is very critical.
According to another conventional method for forming an opening at the bottom electrode below the contact window; i.e., the bottom electrode below the contact window is removed. Hence, even if the gate insulating layer below the contact window is etched through, because the bottom electrode has been removed, no leakage occurs. However, this method requires precise alignment of the opening with the contact window, which is difficult to achieve.